Events

The Five Pitfalls of 4G SOC Design- This webinar explores five significant challenges faced by designers of efficient digital basebands, including pitfalls in LTE's many modes, excessive cost and power, the "million MIPS" hurdle of Turbo decoding, and the dilemma of choosing the right communications among the LTE building blocks. This webinar uses detailed examples from an end-to-end LTE PHY baseband architecture to highlight the key dos and don'ts.

Everything You Wanted to Know about SOC Memory - but Forgot to Ask - This Web seminar discusses the many alternatives for on-chip and off-chip memory usage that SOC designers must understand to develop successful multicore SOCs. The seminar discusses the essentials of SOC memory organizations for multicore designs, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory.

How to Avoid the Traps and Pitfalls of SOC Design - Join Tensilica for an unusually frank discussion of the ways you can avoid the traps and pitfalls and lead your team to a successful SOC design. This Webinar is sure to help you make better SOC design choices. No product pitches. No selling. No boring descriptions of "my wonderful new product." Just hard-headed information you can use to help your design team find its way through the convoluted maze of today's SOC design challenges.

Everything You Wanted to Know About Video Processing - but Were Afraid to See - Product differentiation through video-enhancing features has also become very important. Video pre- and post-processing algorithms (performed before video encoding and after video decoding) are the tools you need to make your HD video offerings stand out in a very crowded market.

Everything You Wanted to Know About Blu-ray Audio - but were afraid to hear - This Webinar provides an in-depth look at the technical aspects of Blu-ray audio that system developers must know. The Webinar will also provide insight into the codecs and the implementation hardware needed for high-quality, multichannel, multi-codec sound reproduction through the smooth, efficient execution of Blu-ray audio-codec firmware.

Untangling the Multicore Mess for SOC Designers - There are many strategies that come into play when trying to meet the diverse needs of such systems with MPSOC (multiple processor system-on-chip) architectures. This presentation provides deep understanding and a framework so that SOC design teams can select the right MPSOC architectures for their specific applications.

Everything You Know About Microprocessors is Wrong - Many system-engineering concepts and "best practices" with respect to system design are no longer valid at the chip level. For example, bus-centric design--made popular by the introduction of the first commercial microprocessor in 1971--continues to dominate on-chip design 36 years later even though nanometer silicon has completely changed the rules of system interconnect. This presentation discusses and openly questions several of these outdated system-design concepts and "best practices".

Selecting Video IP for SOC Design: Ask the Tough Questions - This web seminar discusses the issues revolving around the selection of hardware and software IP used for decoding and encoding video. The field of digital video is in a high state of flux. Our understanding of coder/decoder (codec) issues broadens constantly and new video codecs are introduced regularly. The tradeoffs between packaged video IP blocks and configurable blocks are covered in this Web Seminar as are the reasons for preferring programmable video IP blocks over fixed blocks (codec flexibility being the main reason).

Configurable Processors as Enhanced Application Processors and Controllers - This seminar will show the process of evaluating your code for hot spots and then accelerating those functions using configuration options and the Verilog-like Tensilica Instruction Extension (TIE) language. Whether you are designing a SOC for networking, a wireless system, multimedia, computer peripherals, DSP, or many other functions, you willl learn how to achieve very high performance on those functions, while keeping processor core area very small using Tensilica's Xtensa configurable processor.

Reduce Power and Energy Consumption in Low-Power SOCs through ISA Extension - SOCs designed for low-power applications must extract maximum performance from every microJoule. Configured microprocessor cores help accomplish this objective by greatly reducing the number of cycles needed to execute a task without the need to use manually coded RTL hardware blocks or assembly-language programming. This tutorial presentation explains these concepts in depth by exploring the abilities of configurable processors and through three specific, detailed task examples (AES encryption, Viterbi decoding, and FFTs) that benefit from this design approach.